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| TL594 Precision Switchmode Pulse Width Modulation Control Circuit The TL594 is a fixed frequency, pulse width modulation control circuit designed primarily for Switchmode power supply control. Features http://onsemi.com MARKING DIAGRAMS PDIP-16 N SUFFIX CASE 648 1 * * * * * * * * * Complete Pulse Width Modulation Control Circuitry On-Chip Oscillator with Master or Slave Operation On-Chip Error Amplifiers On-Chip 5.0 V Reference, 1.5% Accuracy Adjustable Deadtime Control Uncommitted Output Transistors Rated to 500 mA Source or Sink Output Control for Push-Pull or Single-Ended Operation Undervoltage Lockout Pb-Free Packages are Available* 16 TL594CN AWLYYWWG 1 16 SO-16 D SUFFIX CASE 751B 1 TL594CDG AWLYWW 1 16 MAXIMUM RATINGS Rating Power Supply Voltage Collector Output Voltage Collector Output Current (Each Transistor) (Note 1) Amplifier Input Voltage Range Power Dissipation @ TA 45C Thermal Resistance Junction-to-Ambient (PDIP) Junction-to-Air (TSSOP) Junction-to-Ambient (SOIC) Operating Junction Temperature Storage Temperature Range Operating Ambient Temperature Range TL594CD, CN, CDTB Derating Ambient Temperature Symbol VCC VC1, VC2 IC1, IC2 VIR PD RqJA 80 140 135 TJ Tstg TA -40 to 85 TA 45 C 125 -55 to +125 C C C Value 42 42 500 -0.3 to +42 1000 Unit V V mA V mW C/W 1 TSSOP-16 DTB SUFFIX CASE 948F 1 TL59 4DTB ALYWG G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS Noninv Input 1 Inv Input 2 Compen/PWN Comp Input 3 Deadtime Control 4 CT 5 Oscillator + Error 1 Amp - + 2 Error Amp - VCC 0.1 V 5.0 V REF Noninv 16 Input Inv 15 Input 14 Vref Output 13 Control 12 VCC 11 C2 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum thermal limits must be observed. RT 6 Q2 Ground 7 C1 8 Q1 10 E2 9 E1 (Top View) *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2005 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 November, 2005 - Rev. 5 Publication Order Number: TL594/D TL594 RECOMMENDED OPERATING CONDITIONS Characteristics Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor) Amplified Input Voltage Current Into Feedback Terminal Reference Output Current Timing Resistor Timing Capacitor Oscillator Frequency PWM Input Voltage (Pins 3, 4, 13) Symbol VCC VC1, VC2 IC1, IC2 Vin lfb lref RT CT fosc - Min 7.0 - - 0.3 - - 1.8 0.0047 1.0 0.3 Typ 15 30 - - - - 30 0.001 40 - Max 40 40 200 VCC - 2.0 0.3 10 500 10 300 5.3 Unit V V mA V mA mA kW mF kHz V ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics REFERENCE SECTION Reference Voltage (IO = 1.0 mA, TA = 25C) (IO = 1.0 mA) Line Regulation (VCC = 7.0 V to 40 V) Load Regulation (IO = 1.0 mA to 10 mA) Short Circuit Output Current (Vref = 0 V) OUTPUT SECTION Collector Off-State Current (VCC = 40 V, VCE = 40 V) Emitter Off-State Current (VCC = 40 V, VC = 40 V, VE = 0 V) Collector-Emitter Saturation Voltage (Note 1) Common-Emitter (VE = 0 V, IC = 200 mA) Emitter-Follower (VC = 15 V, IE = -200 mA) Output Control Pin Current Low State (VOC 0.4 V) High State (VOC = Vref) Output Voltage Rise Time Common-Emitter (See Figure 13) Emitter-Follower (See Figure 14) Output Voltage Fall Time Common-Emitter (See Figure 13) Emitter-Follower (See Figure 14) ERROR AMPLIFIER SECTION Input Offset Voltage (VO (Pin 3) = 2.5 V) Input Offset Current (VO (Pin 3) = 2.5 V) Input Bias Current (VO (Pin 3) = 2.5 V) Input Common Mode Voltage Range (VCC = 40 V, TA = 25C) Inverting Input Voltage Range Open Loop Voltage Gain (DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW) Unity-Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kW) Phase Margin at Unity-Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kW) Common Mode Rejection Ratio (VCC = 40 V) Power Supply Rejection Ratio (DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW) Output Sink Current (VO (Pin 3) = 0.7 V) Output Source Current (VO (Pin 3) = 3.5 V) VIO IIO IIB VICR VIR(INV) AVOL fC m CMRR PSRR IO- IO+ 70 - - 65 - 0.3 -2.0 - - - 2.0 5.0 -0.1 0 to VCC-2.0 -0.3 to VCC-2.0 95 700 65 90 100 0.7 -4.0 - - - - - - - 10 250 -1.0 mV nA mA V V dB kHz deg. dB dB mA mA IC(off) IE(off) VSAT(C) VSAT(E) IOCL IOCH tr - - tf - - 40 40 100 100 100 100 200 200 ns - - - - - - 2.0 - 1.1 1.5 0.1 2.0 100 -100 1.3 2.5 mA - 20 ns mA mA V Vref 4.925 4.9 Regline Regload ISC - - 15 5.0 - 2.0 2.0 40 5.075 5.1 25 15 75 mV mV mA V Symbol Min Typ Max Unit 1. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. http://onsemi.com 2 TL594 ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics PWM COMPARATOR SECTION (Test Circuit Figure 11) Input Threshold Voltage (Zero Duty Cycle) Input Sink Current (VPin 3 = 0.7 V) DEADTIME CONTROL SECTION (Test Circuit Figure 11) Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V) Maximum Duty Cycle, Each Output, Push-Pull Mode (VPin 4 = 0 V, CT = 0.01 mF, RT = 12 kW) (VPin 4 = 0 V, CT = 0.001 mF, RT = 30 kW) Input Threshold Voltage (Pin 4) (Zero Duty Cycle) (Maximum Duty Cycle) OSCILLATOR SECTION Frequency (CT = 0.001 mF, RT = 30 kW) (CT = 0.01 mF, RT = 12 kW, TA = 25C) (CT = 0.01 mF, RT = 12 kW, TA = Tlow to Thigh) Standard Deviation of Frequency* (CT = 0.001 mF, RT = 30 kW) Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25C) Frequency Change with Temperature (DTA = Tlow to Thigh, CT = 0.01 mF, RT = 12 kW) UNDERVOLTAGE LOCKOUT SECTION Turn-On Threshold (VCC Increasing, Iref = 1.0 mA) TA = 25C TA = Tlow to Thigh Hysteresis TL594C,I TL594M TOTAL DEVICE Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) (VCC = 15 V) (VCC = 40 V) Average Supply Current (VPin 4 = 2.0 V, CT = 0.01 mF, RT = 12 kW, VCC = 15 V, See Figure 11) ICC - - - 8.0 8.0 11 15 18 mA - mA Vth 4.0 3.5 VH 100 50 150 150 300 300 5.2 - 6.0 6.5 mV V fosc - 9.2 9.0 fosc Dfosc (DV) Dfosc (DT) - - - 40 10 - 1.5 0.2 4.0 - 10.8 12 - 1.0 - % % % kHz IIB (DT) DCmax 45 - VTH - 0 2.8 - 3.3 - 48 45 50 - V - -2.0 -10 mA % VTH II- - 0.3 3.6 0.7 4.5 - V mA Symbol Min Typ Max Unit *Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, N (Xn - X)2 n=1 N-1 http://onsemi.com 3 TL594 Output Control 13 6 Oscillator RT CT 5 - + 4 Deadtime Control 0.7V - + 0.7mA + 1 - 1 2 3 Feedback PWM Comparator Input 2 PWM Comparator + - 15 16 UV Lockout - + - + 3.5V 14 Ref. Output 7 Gnd 4.9V Reference Regulator 12 VCC Deadtime Comparator Ck D Flip- Flop Q Q2 11 10 Q Q1 8 9 VCC 0.12V Error Amp 1 Error Amp 2 This device contains 46 active transistors. Figure 1. Representative Block Diagram Capacitor CT Feedback/PWM Comp. Deadtime Control Flip-Flop Clock Input Flip-Flop Q Flip-Flop Q Output Q1 Emitter Output Q2 Emitter Output Control Figure 2. Timing Diagram http://onsemi.com 4 TL594 APPLICATIONS INFORMATION Description The TL594 is a fixed-frequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (See Figure 1) An internal-linear sawtooth oscillator is frequency- programmable by two external components, RT and CT. The approximate oscillator frequency is determined by: fosc 1.1 RT * CT common-mode input range from -0.3 V to (VCC - 2 V), and may be used to sense power-supply output voltage and current. The error-amplifier outputs are active high and are ORed together at the noninverting input of the pulse-width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop. Functional Table Input/Output Controls Grounded @ Vref Output Function Single-ended PWM @ Q1 and Q2 Push-pull Operation fout fosc = 1.0 0.5 For more information refer to Figure 3. Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip-flop clock-input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control-signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the Timing Diagram shown in Figure 2.) The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. The deadtime control comparator has an effective 120 mV input offset which limits the minimum output deadtime to approximately the first 4% of the sawtooth-cycle time. This would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output by setting the deadtime-control input to a fixed voltage, ranging between 0 V to 3.3 V. The pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the maximum percent on-time, established by the deadtime control input, down to zero, as the voltage at the feedback pin varies from 0.5 V to 3.5 V. Both error amplifiers have a A VOL, OPEN LOOP VOLTAGE GAIN (dB) f OSC, OSCILLATOR FREQUENCY (Hz) 500 k CT = 0.001 mF VCC = 15 V When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulse-steering flip-flop and inhibits the output transistors, Q1 and Q2. With the output-control connected to the reference line, the pulse-steering flip-flop directs the modulated pulses to each of the two output transistors alternately for push-pull operation. The output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 or Q2, when single-ended operation with a maximum on-time of less than 50% is required. This is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. When higher output-drive currents are required for single-ended operation, Q1 and Q2 may be connected in parallel, and the output-mode pin must be tied to ground to disable the flip-flop. The output frequency will now be equal to that of the oscillator. The TL594 has an internal 5.0 V reference capable of sourcing up to 10 mA of load current for external bias circuits. The reference has an internal accuracy of 1.5% with a typical thermal drift of less than 50 mV over an operating temperature range of 0 to 70C. 100 k 10 k 0.01 mF 1.0 k 500 1.0 k 2.0 k 5.0 k 0.1 mF 10 k 20 k 50 k 100 k 200 k RT, TIMING RESISTANCE (W) 500 k 1.0 M 120 110 100 90 80 70 60 50 40 30 20 10 0 1.0 VCC = 15 V DVO = 3.0 V RL = 2.0 kW AVOL 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 0 20 40 60 80 100 120 140 160 180 1.0 M Figure 3. Oscillator Frequency versus Timing Resistance Figure 4. Open Loop Voltage Gain and Phase versus Frequency http://onsemi.com 5 , EXCESS PHASE (DEGREES) TL594 % DT, PERCENT DEADTIME (EACH OUTPUT) % DC, PERCENT DUTY CYCLE (EACH OUTPUT 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 500 k 1.0 k 10 k 100 k 500 k 0.01 mF CT = 0.001 mF 50 40 2 30 20 10 0 1 VCC = 15 V VOC = Vref 1. C T = 0.01 mF 1. RT = 10 kW 2. C T = 0.001 mF 1. RT = 30 kW 0 1.0 2.0 3.0 3.5 fosc, OSCILLATOR FREQUENCY (Hz) VDT, DEADTIME CONTROL VOLTAGE (IV) Figure 5. Percent Deadtime versus Oscillator Frequency Figure 6. Percent Duty Cycle versus Deadtime Control Voltage 1.9 V CE(sat) , SATURATION VOLTAGE (V) V CE(sat) , SATURATION VOLTAGE (V) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 100 200 300 400 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 IE, EMITTER CURRENT (mA) 0 100 200 300 400 IC, COLLECTOR CURRENT (mA) Figure 7. Emitter-Follower Configuration Output Saturation Voltage versus Emitter Current V TH , UNDERVOLTAGE LOCKOUT THRESHOLD (V) Figure 8. Common-Emitter Configuration Output Saturation Voltage versus Collector Current 10 I CC , SUPPLY CURRENT (mA) 9.8 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 5.0 10 15 20 25 30 VCC, SUPPLY VOLTAGE (V) 35 40 6.0 Turn On 5.5 Turn Off 5.0 4.5 4.0 0 5.0 10 15 20 25 30 IL, REFERENCE LOAD CURRENT (mA) 35 40 Figure 9. Standby Supply Current versus Supply Voltage Figure 10. Undervoltage Lockout Thresholds versus Reference Load Current http://onsemi.com 6 TL594 VCC = 15V VCC Deadtime Feedback RT CT (+) (-) Error (+) (-) Output Control Gnd 150 2W C1 E1 C2 E2 150 2W Output 1 Output 2 + Vin - Error Amplifier Under Test Test Inputs Feedback Terminal (Pin 3) + Vref - 50k Other Error Amplifier Ref Out Figure 11. Error-Amplifier Characteristics Figure 12. Deadtime and Feedback Control Circuit 15V RL 68 C Each Output Transistor Q E CL 15pF VC Each Output Transistor Q E RL 68 CL 15pF VEE 15V C 90% VCC 10% tr tf 90% 10% 90% 90% VEE 10% 10% Gnd tr tf Figure 13. Common-Emitter Configuration Test Circuit and Waveform Figure 14. Emitter-Follower Configuration Test Circuit and Waveform http://onsemi.com 7 TL594 VO Vref To Output Voltage of System 3 1 + - 2 R2 Positive Output Voltage VO = Vref 1+ R1 R2 Error Amp 3 Error Amp 1 R2 R1 + - 2 Negative Output Voltage VO = Vref R1 R2 R1 VO To Output Voltage of System Vref Figure 15. Error-Amplifier Sensing Techniques Output Control Output Q RT 6 5 CT Vref DT R1 4 R2 30k 0.001 Output Q 80 Vref DT 4 RS CS Max. % on Time, each output 45 - R1 1+ R2 Figure 16. Deadtime Control Circuit Figure 17. Soft-Start Circuit C1 QC Q1 Output Control Single-Ended C2 0 VOC 0.4 V Q2 E2 Q2 QE E1 1.0 mA to 500 mA Output Control Push-Pull 2.4 V VOC Vref Q1 C1 E1 1.0 mA to 250 mA C2 E2 1.0 mA to 250 mA Figure 18. Output Connections for Single-Ended and Push-Pull Configurations http://onsemi.com 8 TL594 Vref 6 5 RT CT RT Master CT RS Vref Vin > 40V 1N975A VZ = 39V RT Slave (Additional Circuits) 270 5.0V Ref Gnd 7 VCC 12 6 5 CT Figure 19. Slaving Two or More Control Circuits Figure 20. Operation with Vin > 40 V Using External Zener +Vin = 8.0V to 20V 12 1 2 1.0M 33k 0.01 0.01 3 15 16 + - Comp - + OC 13 4.7k 4.7k VREF DT 14 + 10 10k 15k 0.001 4 5 CT 6 RT Gnd 7 9 E1 10 E2 TL594 C2 11 Tip 32 47 VCC C1 8 47 Tip 32 + 50 25V 1N4934 240 T1 1N4934 22 k + 50 35V 4.7k 1.0 +VO = 28V IO = 0.2A L1 + 50 35V All capacitors in mF Figure 21. Pulse Width Modulated Push-Pull Converter Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 10 V to 40 V Vin = 28 V, IO = 1.0 mA to 1.0 A Vin = 28 V, IO = 1.0 A Vin = 28 V, RL = 0.1 W Vin = 28 V, IO = 1.0 A Results 14 mV 0.28% 3.0 mV 0.06% 65 mVpp P.A.R.D. 1.6 A 71% L1 - 3.5 mH @ 0.3 A T1 - Primary: 20T C.T. #28 AWG T1 - Secondary: 12OT C.T. #36 AWG T1 - Core: Ferroxcube 1408P-L00-3CB http://onsemi.com 9 TL594 1.0mH @ 2.0A +Vin = 10V to 40V Tip 32A +VO = 5.0V IO = 1.0A 47 150 47k 0.1 C2 Comp - 50 50V + + 3 2 1 14 MR850 5.1k 500 10V + 5.1k 5.1k 1.0M 12 VCC 8 C1 11 TL594 Vref CT 5 RT 6 D.T. O.C. Gnd E1 4 13 7 9 E2 10 - 15 16 + + 150 50 10V 0.001 47k 0.1 Figure 22. Pulse Width Modulated Step-Down Converter Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 8.0 V to 40 V Vin = 12.6 V, IO = 0.2 mA to 200 mA Vin = 12.6 V, IO = 200 mA Vin = 12.6 V, RL = 0.1 W Vin = 12.6 V, IO = 200 mA Results 3.0 mV 5.0 mV 40 mVpp 72% 0.01% 0.02% P.A.R.D. 250 mA ORDERING INFORMATION Device TL594CD TL594CDG TL594CDR2 TL594CDR2G TL594CN TL594CNG TL594CDTBG* TL594CDTBR2G Operating Temperature Range -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) TSSOP-16* TSSOP-16* Shipping 48 Units/Rail 48 Units/Rail 2400 Tape & Reel 2400 Tape & Reel 25 Units/Rail 25 Units/Rail 96 Units/Rail 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 10 TL594 PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE T -A- 16 9 B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 11 TL594 PACKAGE DIMENSIONS TSSOP-16 DTB SUFFIX CASE 948F-01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 12 CCC EEE CCC EEE CCC M K1 SECTION N-N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M TL594/D |
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